Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
NMI Enable (GPI_NMI_EN_GPP_B_0) – Offset 2d0
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:25 | 0h | RO | Reserved |
24 | 0h | RO | GPI NMI Enable (GPI_NMI_EN_ishi3c0_clk_loopbk) This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0 = disable NMI generation 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is '1', bit0 of this bit is locked down to read-only. Bit assignment: Bit0 = Pad 0 Bit1 = Pad 1 Bit2 = Pad 2 ... Bit N-1 = Pad N-1 For pads which do not support NMI, the corresponding bit is read-only zero. \t\t\t |
23 | 0h | RW | GPI NMI Enable (GPI_NMI_EN_xxgpp_b_23) This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0 = disable NMI generation 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is '1', bit0 of this bit is locked down to read-only. Bit assignment: Bit0 = Pad 0 Bit1 = Pad 1 Bit2 = Pad 2 ... Bit N-1 = Pad N-1 For pads which do not support NMI, the corresponding bit is read-only zero. \t\t\t |
22:21 | 0h | RO | Reserved |
20 | 0h | RW | GPI NMI Enable (GPI_NMI_EN_xxgpp_b_20) This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0 = disable NMI generation 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is '1', bit0 of this bit is locked down to read-only. Bit assignment: Bit0 = Pad 0 Bit1 = Pad 1 Bit2 = Pad 2 ... Bit N-1 = Pad N-1 For pads which do not support NMI, the corresponding bit is read-only zero. \t\t\t |
19:15 | 0h | RO | Reserved |
14 | 0h | RW | GPI NMI Enable (GPI_NMI_EN_xxgpp_b_14) This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0 = disable NMI generation 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is '1', bit0 of this bit is locked down to read-only. Bit assignment: Bit0 = Pad 0 Bit1 = Pad 1 Bit2 = Pad 2 ... Bit N-1 = Pad N-1 For pads which do not support NMI, the corresponding bit is read-only zero. \t\t\t |
13:0 | 0h | RO | Reserved |