Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Interrupter Moderation (IMOD0) – Offset 2024
The register listed in this section is at offset 2024h for IMOD0.
There are a total of 8 IMOD registers at the following offsets:
IMOD0 : at offset 2024h
IMOD1: at offset 2044h
IMOD2: at offset 2064h
.....
IMOD6: at offset 20E4h
IMOD7; at offset 2104h
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RW | Interrupt Moderation Counter (IMODC) Down counter. Loaded with Interval Moderation value—value of bits 15:0, whenever the IP bit is cleared to 0b, counts down to ‘0’, and stops. The associated interrupt shall be signaled whenever this counter is ‘0’, the Event Ring is not empty, the IE and IP bits = 1, and EHB = 0. |
15:0 | fa0h | RW | Interrupt Moderation Interval (IMODI) Minimum inter-interrupt interval. The interval is specified in 250 ns increments. A value of ‘0’ disables interrupt throttling logic and interrupts shall be generated immediately if IP = 0, EHB = 0, and the Event Ring is not empty. |