Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SMBUS_PIN_CTL Register (SMBC) – Offset f
Note: This register is in the resume well and is reset by RSMRST#
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7:3 | 0h | RO | Reserved |
2 | 1h | RW | SMBCLK_CTL (SMBCLK_CTL) 0 = The controller will drive the SMBCLK pin low, independent of what the other SMB logic would otherwise indicate for the SMBCLK pin. |
1 | 0h | RO/V | SMBDATA_CUR_STS (SMBDATA_CUR_STS) This bit has a default value that is dependent on an external signal level. This returns the value on the SMBDATA pin. It will be 1 to indicate high, 0 to indicate low. This allows software to read the current state of the pin. |
0 | 0h | RO/V | SMBCLK_CUR_STS (SMBCLK_CUR_STS) This bit has a default value that is dependent on an external signal level. This returns the value |