Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Register A (Register_A) – Offset a
RTC Index: 0Ah
Attribute: Read/Write
Default Value: 0UUUUUUU
Size: 8-bit
Lockable: No Power
Well: RTC
This register is used for general configuration of the RTC functions. None of the bits
are affected by RSMRST# or any other reset signal.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7 | 0h | RO/V | UPDATE IN PROGRESS (UIP) This bit may be monitored as a status flag. When asserted as a 1, the update is soon to occur or is in progress. If 0, the update cycle will not start for at least 488 s. The time, calendar, and alarm information in RAM is always available when the UIP bit is 0. |
6:4 | 7h | RW | Division Chain Select (DV_2_0) These three bits control the divider chain for the oscillator, and are not affected by RSMRST# or any other reset signal. DV(2) corresponds to bit 6. |
3:0 | 0h | RW | Rate Select (RS_3_0) Selects one of 13 taps of the 15 stage divider chain. The selected tap can generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be used, these bits should all be set to zero. RS3 corresponds to bit 3. |