Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SLP S0 DEBUG REG2 (SLP_S0_DBG_2) – Offset 10bc
This register captures the state of low power events involved in SLP_S0# entry to assist with debug. The status is captured as part of C10 entry(once CPU has entered package C10) or it can be captured by writing a 1 to LATCH_SLPS0_EVENTS bit in SLP_S0_DEBUG_REG0 register.Note that static or function disable status of the IP is incorporated in the individual status register bits though overrides / masks in CPPMVRIC* registers does not impact the value reflects in this register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:15 | 0h | RO | Reserved |
14 | 0h | RO/V | PMC ARC PG Ready IDLE (PMC_ARC_IDLE_STS) This bit when 1 indicates that the PMCs ARC microcontroller is ready for power gating |
13 | 0h | RO/V | Platform ASLT greater than threshold Status (ASLT_GT_THRES_STS) This bit when 1 indicates that the platform ASLT is greater than threashold |
12 | 0h | RO/V | PM_SYNC States Inactive (PMSYNC_STATE_IDLE_STS) This bit when 1 indicates that PMSYNC requests are not active. |
11 | 0h | RO | Reserved |
10 | 0h | RO/V | CNV VNN REQ Status (CNV_VNN_REQ_STS) This bit when 1 indicates that CNV VNN Req is active. |
9 | 0h | RO/V | CNV VNN AON REQ Status (CNV_VNNAON_REQ_STS) This bit when 1 indicates that CNV VNNAON Req is active. |
8 | 0h | RO/V | ISH VNN REQ Status (ISH_VNN_REQ_STS) This bit when 1 indicates that ISH Vnn Req is active. |
7 | 0h | RO/V | ISH VNN AON REQ Status (ISH_VNNAON_REQ_STS) This bit when 1 indicates that ISH VnnAON Req is active. |
6 | 0h | RO/V | PCIe Low Power Status (PCIE_LP_STS) This bit when 1 indicates that all PCIe root port controllers are in their low power state. |
5 | 0h | RO/V | Thermal Sensor Disabled Status (TS_DIS_STS) This bit when 1 indicates that the thermal sensor is disabled |
4 | 0h | RO/V | GBE No Link Status (GBE_NO_LINK_STS) This bit when 1 indicates that the GBE interface is disconected. |
3 | 0h | RO | Reserved |
2 | 0h | RO/V | USB2 SUS Power Gated Status (USB2_SUS_PG_STS) This bit when 1 indicates that USB2 PHY SUS power domain is off. |
1 | 0h | RO/V | CSME Power Gated Status (CSME_PG_STS) This bit when 1 indicates that all power gated domains in CSME are turned off. |
0 | 0h | RO/V | MHPY CORE Power Gated Status (MPHY_CORE_PG_STS) This bit when 1 indicates that HSIO core and data lanes are off. |