Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Reset Control Register (RST_CNT) – Offset cf9
Reset Control register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7:4 | 0h | RSV | Reserved (RSVD) Reserved |
3 | 0h | RW | Full Reset (FULL_RST) When this bit is set to 1 and bit 1 is set to 1 (indicating Hard Reset, not Soft Reset), and the RST_CPU bit (bit 2) is written from 0 to 1, the processor will do a full reset, including driving SLP_S3#, SLP_S4# and SLP_S5# active (low) for at least 3 (and no more than 5) seconds. |
2 | 0h | RW | Reset CPU (RST_CPU) This bit will cause either a hard or soft reset to the CPU depending on the state of the SYS_RST bit (bit 1 in this same register). The software will cause the reset by setting bit 2 from a 0 to a 1. |
1 | 0h | RW | System Reset (SYS_RST) Ths bit determines the type of reset caused via RST_CPU (bit 2 of this register). If SYS_RST is 0 when RST_CPU goes from 0 to 1, then INIT# will be forced active for 16 PCI clocks. If SYS_RST is 1 when RST_CPU goes from 0 to 1, then PCI reset will be forced active for about 1 ms, however the SLP_S3#, SLP_S4# and SLP_S5# signals assertion is dependent on the value of the FULL_RST (bit3 of this register). |
0 | 0h | RSV | Reserved (RSVD_1) Reserved |