Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
eSPI Device Configuration Register Data (SLV_CFG_REG_DATA) – Offset 4004
Along with SLV_CFG_REG_CTL, this register controls Rd/Wr access to Device Configuration registers using eSPI Get/Set_Configuration cycles. It allows access to Device configuration registers from Host/CSME software/firmware.
For writes (SCRT = 2'b01) to Device Configuration registers, this register should be written to first with the required data before writing to the CTL register. The eSPI-MC processes the write to the Device using an eSPI Set_Configuration command.
If a write is to a supported register in the reserved register address range (0h 7FFh), the eSPI-MC updates its local copy of the Device configuration registers after the write has been successfully sent to the Device.
Note: eSPI controller does no checking of the register values (even for supported Device Capabilities / Configuration Registers). SW assumes full responsibility for programming values supported by both the eSPI controller and the Device.
For reads (SCRT = 2'b00 or 2b10) to Device Configuration registers, the hardware writes the data read back from the Device into this register. The read data is valid after hardware has cleared the SCRE bit in the CTL register and the SCRS field indicates a successful transaction.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:0 | 0h | RW/V | Device Configuration Register for Read and Write data (SCRD) Configuration register Write data from software or read data from the device. |