Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Device Idle Control Register (THC_M_CMN_DEVIDLECTRL) – Offset 10
Device Idle Control Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:5 | 0h | RO | Reserved (RSVD_31_5) Reserved. |
4 | 0h | RO | Interrupt Request Capable (IRC) Set to 1 by HW if it is capable of generating an interrupt on command completion, else 0. |
3 | 1h | RW/1C/V | Restore Required bit (RR) When set (by HW), SW must restore state to the IP. The state may have been lost due to a reset or full power lost. SW clears the bit by writing a 1. This bit will be set on initial power up. |
2 | 0h | RW | Dev Idle (DEVIDLE) SW sets this bit to 1 to move the function into the DevIdle state. Writing this bit to 0 will return the function to the fully active D0 state (D0i0) |
1 | 0h | RO | Interrupt Request (IR) SW sets this bit to 1 to ask for an interrupt to be generated on completion of the command. SW must clear or set this on each write to this register. |
0 | 0h | RO/V | Command in Progress (CIP) HW sets this bit on a 1-0 or 0-1 transition of bit [2]. While set, the other bits in this register are not valid and it is illegal for SW to write to any bit in this register. When clear all the other bits in the register are valid and SW may write to any bit. If Interrupt Request bit [1] was set for the current command, HW may clear this bit before the interrupt has been made visible to SW, since when SW actually handles a particular interrupt is not visible to the HW. SW writes to this bit have no effect. |