Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
D0i3 and Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) – Offset a0
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:22 | 0h | RO | Reserved Field (RESERVED0) Reserved |
21 | 0h | RW/P | HAE Field (HAE) Hardware Autonomous Enable |
20 | 0h | RO | Reserved Field (RESERVED1) Reserved |
19 | 0h | RW/P | Sleep Enable Field (SLEEP_EN) Sleep Enable |
18 | 0h | RW/P | D3 Hen Field (D3HEN) DEVIDLE Enable (DEVIDLEN): If ?1? then the function will power gate when idle and the DevIdle register (DevIdleC[2] = ?1?) is set. |
17 | 0h | RW/P | Device Idle En Field (DEVIDLEN) PMCRE: PMC Request Enable |
16 | 0h | RW/P | PMC Request Enable Field (PMCRE) D3-Hot Enable (D3HEN): If ?1? then function will power gate when idle and the PMCSR[1:0] register in the function =?11? (D3). |
15:13 | 0h | RO | Reserved Field (RESERVED2) Reserved |
12:10 | 2h | RW/O/P | Power Latency Scale Field (POW_LAT_SCALE) Power On Latency Scale |
9:0 | 0h | RW/O/P | Power Latency Value Field (POW_LAT_VALUE) Power On Latency value |