Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
System Time Control High Register (LTRCAP) – Offset a8
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 0h | RO | Reserved |
28:26 | 0h | RW | Maximum Non-Snoop Latency Scale (MNSLS) Provides a scale for the value contained |
25:16 | 0h | RW | Maximum Non-Snoop Latency (MNSL) Specifies the maximum non-snoop latency that a |
15:13 | 0h | RO | Reserved |
12:10 | 0h | RW | Maximum Snoop Latency Scale (MSLS) Provides a scale for the value contained within |
9:0 | 0h | RW | Maximum Snoop Latency (MSL) Specifies the maximum snoop latency that a device is |