Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
DMA Position Lower Base Address (DPLBASE) – Offset 70
This register specifies the base address (lower 32 bits) of DMA Position Buffer.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:7 | 0h | RW | DMA Position Lower Base Address (DPLBASE) Lower 32 bits of the DMA Position Buffer Base Address. This register field must not be written when any DMA engine is running or the DMA transfer may be corrupted. This same address is used by the Flush Control, and must be programmed with a valid value before the FLCNRTL bit is set. |
6:1 | 0h | RO | Reserved |
0 | 0h | RW | DMA Position Buffer Enable (DPBE) When this bit is set to a 1, the controller will write the DMA positions of each of the DMA engines to the buffer in main memory periodically (typically once/frame). Software can use this value to know what data in memory is valid data.The controller must guarantee that the values in the DMA Position Buffer that the software can read represent positions in the stream for which valid data exists in the Streams DMA buffer. This has particular relevance in systems which support isochronous transfer- the stream positions in the software-visible memory buffer must represent stream data which has reached the Global Observation point. |