Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
GPI Interrupt Status (GPI_IS_GPP_S_0) – Offset 200
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:8 | 0h | RO | Reserved (RSVD_0)
|
7 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_s_7) Same description as bit 0. |
6 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_s_6) Same description as bit 0. |
5 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_s_5) Same description as bit 0. |
4 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_s_4) Same description as bit 0. |
3 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_s_3) Same description as bit 0. |
2 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_s_2) Same description as bit 0. |
1 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_s_1) Same description as bit 0. |
0 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_s_0) This bit is set to '1' by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: |