Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Link Status Register (LNKSTS) – Offset 92
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:13 | 0h | RO | Reserved (RSVD) Reserved |
12 | 0h | RW/O | Slot clock configuration (SCC) This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear. This bit is not used and is not connected to any logic. |
11 | 0h | RO | Link Training (LT) This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state. This bit is not applicable and Reserved for Endpoints |
10 | 0h | RO | Training Error (TR) This read-only bit indicates that a Link training error occurred. This field is not applicable and reserved for Endpoint devices |
9:4 | 1h | RO | Negotiated Link Width (NLW) This field indicates the negotiated width of the given PCI Express Link.Defined encodings are: |
3:0 | 1h | RO | Current Link Speed (CLS) This field indicates the negotiated Link speed of the given PCI Express Link. |