Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Command Register (CMD) – Offset 4
Command Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:11 | 0h | RO | Reserved (RSVD) Reserved |
10 | 0h | RW | Interrupt Disable (INTD) 1 = Disables SMBus to assert its PIRQB# signal. Defaults to 0. |
9 | 0h | RO | Fast Back to Back Enable (FBE) Reserved as 0. Read Only. |
8 | 0h | RW | SERR# Enable (SERRE) 1 = Enables SERR# generation |
7 | 0h | RO | Wait Cycle Control (WCC) Reserved as 0. Read Only. |
6 | 0h | RW | Parity Error Response (PER) 1 = Sets Detected Parity Error bit when parity error is detected |
5 | 0h | RO | VGA Palette Snoop (VGAPS) Reserved as 0. Read Only. |
4 | 0h | RO | Postable Memory Write Enable (PMWE) Reserved as 0. Read Only. |
3 | 0h | RO | Special Cycle Enable (SCE) Reserved as 0. Read Only. |
2 | 0h | RO | Bus Master Enable (BME) Reserved as 0. Read Only. |
1 | 0h | RW | Memory Space Enable (MSE) 1= Enables memory mapped config space. |
0 | 0h | RW | I/O Space Enable (IOSE) 1= enables access to the SM Bus I/O space registers as defined by the Base Address Register. |