Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Input Stream Descriptor x Control (ISD0CTL_B2) – Offset 82
This register provides the control of the input stream DMA.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7:4 | 0h | RW | Stream Number (STRM) This value reflects the Tag associated with the data being transferred on the link.0000=Reserved (Indicates Unused)0001=Stream 11110=Stream 141111=Stream 15When an input stream is detected on any of the SDIx signals that match this value, the data samples are loaded into the FIFO associated with this descriptor. Note that while a single SDIx input may contain data from more than one stream number, two different SDIx inputs may not be configured with the same stream number. |
3 | 0h | RO | Bidirectional Direction Control (DIR) This bit is only meaningful for Bidirectional streams. Therefore this bit is hardwired to 0. |
2 | 1h | RO | Traffic Priority (TP) Hardwired to 1 indicating that all streams will use VC1 if it is enabled throughout the PCI Express registers. |
1:0 | 0h | RO | Stripe Control (STRIPE) This field is meaningless for input streams. |