Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG MCR (MCR) – Offset 10
Modem Control Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:6 | 0h | RO | Reserved |
5 | 0h | RW | AFCE (AFCE) Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always |
4 | 0h | RO | Reserved |
3 | 0h | RW | OUT2 (OUT2) OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 out2_n de-asserted (logic 1) 1 out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to 1), the out2_n output is held inactive high while the value of this location is internally looped back to an input. |
2 | 0h | RW | OUT1 (OUT1) OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 out1_n de-asserted (logic 1) 1 out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to 1), the out1_n output is held inactive high while the value of this location is internally looped back to an input. |
1 | 0h | RW | RTS (RTS) Request to Send. This is used to directly control the Request to Send (rts_n) output. |
0 | 0h | RW | DTR (DTR) Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 dtr_n de-asserted (logic 1) 1 dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to 1), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. |