Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
THC LTR Control Register (THC_M_CMN_LTR_CTRL) – Offset 14
THC LTR Control Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:30 | 3h | RO/V | Last LTR Message Sent (LAST_LTR_SENT) This field reflects the last LTR message that was sent by the THC hardware. |
29:20 | 0h | RW | Active Latency Value (ACT_LTR_VAL) The agent's latency tolerance is this value multiplied by ACT_LTR_SCALE. |
19:17 | 0h | RW | Active Latency Scale (ACT_LTR_SCALE) Specifies the scale for the value reported in the ACT_LTR_VAL field. Encodings: |
16:7 | 0h | RW | Low Power Latency Value (LP_LTR_VAL) The agent's latency tolerance is this value multiplied by LP_LTR_SCALE. |
6:4 | 0h | RW | Low Power Latency Scale (LP_LTR_SCALE) Specifies the scale for the value reported in the LP_LTR_VAL field. Encodings: |
3 | 0h | RW | Enable sending Low power LTR to PMC. (LP_LTR_EN) If this bit is written to 1 then the THC will send a low power LTR message with value of LP_LTR_VAL multiplied by LP_LTR_SCALE if LP_LTR_REQ is 1, else will send an infinite LTR message. If this bit is written to 0 then the THC does not send low power LTR message. This is normally used by software to send LTR when it moves the THC devices to low power state like ARMed, Doze or Sleep. |
2 | 0h | RW | Low Power LTR Requirement (LP_LTR_REQ) If this bit is set to 1 then the agent's low power latency tolerance is LP_LTR_VAL multiplied by LP_LTR_SCALE. |
1 | 0h | RO | Reserved |
0 | 0h | RW | Active LTR Requirement (ACTIVE_LTR_REQ) If this bit is set to 1 then the agent's latency tolerance is ACT_LTR_VAL multiplied by ACT_LTR_SCALE. |