Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Device Control (DEVC) – Offset 88
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0h | WO | Initiate FLR (IF) Used to initiate FLR transition. A write of 1 initiates FLR transition. Since hardware must not respond to any cycles until FLR completion, the read value by software from this bit is 0. |
14:12 | 2h | RW | Max Read Request Size (MRRS) This field sets the maximum Read Request size for the Function as a Requester. The Function must not generate Read Requests with size exceeding the set value. |
11 | 1h | RW | Enable No Snoop (NSNPEN) When set to 1 (or EM2.FNSNPEN = 1) the ACE IP is permitted to set the No Snoop bit in the Requester Attributes of a bus master transaction. In this case VC0 or VC1 may be used for isochronous transfers. |
10 | 0h | RO | Auxiliary (AUX) Hardwired to 0 indicating the IP does not draw AUX power (outside of PME usage). |
9 | 0h | RO | Phantom Functions Enable (PFEN) Hardwired to 0 disabling phantom functions. |
8 | 0h | RO | Extended Tag Field Enable (ETEN) Hardwired to 0 enabling 5-bit tag. |
7:5 | 0h | RO | Max Payload Size (MAXPAY) Hardwired to 000 indicating 128 B. |
4 | 0h | RO | Enable Relaxed Ordering (ROEN) Hardwired to 0 disabling relaxed ordering. |
3 | 0h | RW | Unsupported Request Reporting Enable (URREN) This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages. |
2 | 0h | RW | Fatal Error Reporting Enable (FEREN) Functionality not implemented. This bit is RW to pass PCI Express compliance testing. |
1 | 0h | RW | Non-Fatal Error Reporting Enable (NFEREN) This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages. |
0 | 0h | RW | Correctable Error Reporting Enable (CEREN) Functionality not implemented. This bit is RW to pass PCI Express compliance testing. |