Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Global Reset Causes 0 (GBLRST_CAUSE0) – Offset 1924
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW/1C/V | IOE Global Reset Cause (IOE_GRST_TRIGGER) If bit is set to 1, the last global reset was caused by an IOE global reset trigger. |
31 | 0h | RW/1C/V | IOE PMC Type 8 Global Reset Cause (IOE_SOC_PMC_TYPE_8_GRST_TRIGGER) If bit is set to 1, the last global reset was caused by an IOE PMC type 8 global reset trigger. |
30 | 0h | RW/1C/V | ESE Global Reset Cause (ESE_GBLRST_REQ) If bit is set to 1, the last global reset was caused by a security global reset request. |
29 | 0h | RO | Reserved |
28 | 0h | RW/1C/V | IOE Thermal Global Reset Cause (IOE_THRM) If bit is set to 1, the last global reset was caused by IOE thermal. |
27 | 0h | RO | Reserved |
26 | 0h | RW/1C/V | Graphics Thermal Global Reset Cause (GFX_THRM) If bit is set to 1, the last global reset was caused by graphics thermal. |
25 | 0h | RW/1C/V | Compute Tile Thermal Global Reset Cause (COMPUTE_THRM) If bit is set to 1, the last global reset was caused by compute tile thermal. |
24 | 0h | RO | Reserved |
23 | 0h | RW/1C/V | PMC ROM Parity Global Reset Cause (PMC_IROM_PARITY) If bit is set to 1, the last global reset was caused by PMC ROM parity. |
22 | 0h | RW/1C/V | PMC SRAM Global Reset Cause (PMC_SRAM_UNC_ERR) If bit is set to 1, the last global reset was caused by PMC SRAM uncorrrectable errors. |
21:20 | 0h | RO | Reserved |
19 | 0h | RW/1C/V | Over Clocking WDT Global Reset Cause (OCWDT_NOICC) If bit is set to 1, the last global reset was caused by over clocking watchdog timer expired. |
18 | 0h | RO | Reserved |
17 | 0h | RW/1C/V | CSME Uncorrectable Error Global Reset Cause (ME_UNC_ERR) If bit is set to 1, the last global reset was caused a CSME uncorrectable error. |
16:14 | 0h | RO | Reserved |
13 | 0h | RW/1C/V | ISH Global Reset Cause (ISH) If bit is set to 1, the last global reset was caused by ISH. |
12 | 0h | RW/1C/V | SYS_PWROK Global Reset Cause (SYSPWR_FLR) If bit is set to 1, the last global reset was caused by SYS_PWROK going low in S0. |
11 | 0h | RW/1C/V | Power Failure Global Reset Cause (PCHPWR_FLR) If bit is set to 1, the last global reset was caused by PLT_PWROK going low in S0. |
10 | 0h | RW/1C/V | PMC FW Global Reset Cause (PMC_FW) If bit is set to 1, the last global reset was caused by PMC FW. |
9 | 0h | RW/1C/V | CSME WDT Global Reset Cause (ME_WDT) If bit is set to 1, the last global reset was caused by CSME watchdog timer expired. |
8 | 0h | RW/1C/V | PMC WDT Global Reset Cause (PMC_WDT) If bit is set to 1, the last global reset was caused by PMC watchdog timer expired. |
7 | 0h | RO | Reserved |
6 | 0h | RW/1C/V | CSME Global Reset Cause (MEGBL) If bit is set to 1, the last global reset was caused by a CSME global reset (with details reflected in GBLRST_CAUSE1 register). |
5 | 0h | RW/1C/V | SoC North Thermal Global Reset Cause (SOCN_THRM) If bit is set to 1, the last global reset was caused by the SoC north tile thermal. |
4 | 0h | RW/1C/V | CSME Power Button Override Global Reset Cause (ME_PBO) If bit is set to 1, the last global reset was caused by CSME power button override. |
3 | 0h | RW/1C/V | SoC South Thermal Global Reset Cause (SOCS_THRM) If bit is set to 1, the last global reset was caused by the SoC South tile thermal. |
2 | 0h | RW/1C/V | PMC Uncorrectable Error Global Reset Cause (PMC_UNC_ERR) If bit is set to 1, the last global reset was caused by a PMC uncorrectable error. |
1 | 0h | RW/1C/V | Power Button Override Global Reset Cause (PBO) If bit is set to 1, the last global reset was caused by power button override. |
0 | 0h | RW/1C/V | Security Policy Error Global Reset Cause (SECURE_POLICY_ERR) If bit is set to 1, the last global reset was caused by a security policy error. |
0 | 0h | RW/1C/V | IOE PMC Type 7 Global Reset Cause (IOE_SOC_PMC_TYPE_7_GRST_TRIGGER) If bit is set to 1, the last global reset was caused by an IOE PMC type 7 global reset trigger. |