Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Device Activity Status Register (DEVTRAP_STS) – Offset 44
Lockable: No Usage: Legacy Only Power Well: Primary
Each bit indicates if an access has occurred to the corresponding device's trap range, or for bits 6:9 if the corresponding PCI interrupt is active. Write 1 to the same bit position to clear it. This register is used by APM power management software to see if there has been system activity. The periodic SMI# timer indicates if it is the right time to read the DEVTRAP_STS register.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | Reserved (RSVD_31_16) Reserved |
15:14 | 0h | RO | Reserved (RSVD_15_14) Reserved |
13 | 0h | RO | Reserved (RSVD_13) Reserved |
12 | 0h | RW/1C/V | D12 Trap Status (D12_TRP_STS) KBC (60/64h) |
11:10 | 0h | RO | Reserved (RSVD_11_10) Reserved |
9 | 0h | RW/1C/V | D9 Trap Status (D9_TRP_STS) PIRQ[D or H] |
8 | 0h | RW/1C/V | D8 Trap Status (D8_TRP_STS) PIRQ[C or G] |
7 | 0h | RW/1C/V | D7 Trap Status (D7_TRP_STS) PIRQ[B or F] |
6 | 0h | RW/1C/V | D6 Trap Status (D6_TRP_STS) PIRQ[A or E] This bit will be set if PCI IRQ A or PCI IRQ E goes active (by the pin or internal signal). |
5 | 0h | RW/1C/V | D5 Trap Status (D5_TRP_STS) This will be set if any of the following are accessed (as determined by the I/O ranges in the LPC decoder (even if the LPC forwarding is not enabled): SP1, SP2, PP, FDC. |
4:1 | 0h | RO | Reserved (RSVD_4_1) Reserved |
0 | 0h | RW/1C/V | D0 Trap Status (D0_TRP_STS) The access/SMI was due to the SATA logic. There is no corresponding bit in the DEVTRAP_EN register because the enables are in the new SATA registers. See SATA C-Spec Chapter for details. |