Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Management Configuration Reg 2 (PM_CFG2) – Offset 183c
This register contains misc. fields used to configure the processor power management behavior.
This register is in multiple power wells and reset domains (see below).
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 0h | RW | Power Button Override Period (PBOP) This field determines, while the power button remains asserted, how long the PMC |
28 | 0h | RW/L | Power Button Native Mode Disable (PB_DIS) When this bit is '0' (default), the PMC's power button logic will act upon the input value |
27 | 0h | RO | Reserved |
26 | 0h | RW/V | DRAM_RESET# Control (DRAM_RESET_CTL) BIOS uses this bit to control the DRAM_RESET# pin, which is routed to the reset pin on the DRAM. |
25:0 | 0h | RO | Reserved |