Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
TCO1_CNT Register (TCTL1) – Offset 8
TCO1_CNT Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:13 | 0h | RO | Reserved (RSVD) Reserved |
12 | 0h | RW | TCO_LOCK (TCO_LOCK) When set to 1, this bit prevents writes from changing the TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. A core-well reset is required to change this bit from 1 to 0. This bit defaults to 0. |
11 | 0h | RW | TCO_TMR_HALT (TCO_TMR_HALT) 1 = The TCO timer will halt. It will not count, and thus cannot reach a value that would cause an SMI# or to cause the SECOND_TO_STS bit to be set. This will also prevent rebooting. |
10 | 0h | RO | Reserved |
9 | 0h | RW | NMI2SMI_EN (NMI2SMI_EN) Setting this bit 1 forces all NMIs to instead cause an SMI#, and will be reported in the TCO1_STS register. NMI2SMI_EN bit is set AND the NMI_EN# bit is set to 0, the NMI# will be routed to cause an SMI#. No NMI will be caused. However, if the GBL_SMI_EN bit is not set, then no SMI# will be generated, either. If NMI2SMI_EN is set but the NMI_EN# bit is set to 1, then no NMI or SMI# will be generated. The following table shows the possible combinations: |
8 | 0h | RW | NMI_NOW (NMI_NOW) Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force entry to the NMI handler. The NMI handler is expected to clear this bit. Another NMI will not be generated until the bit is cleared by writing a 1 back to the same bit position. |
7:1 | 0h | RO | Reserved (RSVD_1) Reserved |
0 | 0h | RW | NO_REBOOT_MSUS (NR_MSUS) This bit reflects the No Reboot pin strap state. It is sampled high on PWROK. This bit may be set or cleared by software if the strap is sampled low but may not override the strap when the it indicates No Reboot. |