Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SW LTP Pointer (CNVI_WIFI_LTP_PTR) – Offset 16c
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:20 | 0h | RO | SWLTRLOC (SWLTRLOC) SW LTR Update MMIO Offset Location |
19:4 | 0h | RO | Reserved |
3:1 | 0h | RO | BARNUM (BARNUM) Base Address Register Number. Contains the 0's based AR Number of the BAR which contains the location of the SW LTR MMIO register. |
0 | 0h | RO | Value Identification (VALID) Set to '1' to indicate that the function has implemented a SW LTR register as specified in the DevIdle that can be located using the SWLTRLOC register and BARNUM. Set to '0' to indicate that the function has not implemented a SW LTR register that is compliant to the DevIdle definition. This could be because the function has not implemented SW LTR at all, or has a device specific version of SW LTR. Need to be fixed to 1'b0 |