Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Status And Command (STATUSCOMMAND) – Offset 4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:30 | 0h | RO | Reserved Field (RESERVED0) This field is This field is Reserved 0 |
29 | 0h | RW/1C | Rma Field (RMA) Received Master Abort |
28 | 0h | RW/1C | Rta Field (RTA) Received Target Abort |
27:21 | 0h | RO | Reserved Field (RESERVED1) This field is Reserved |
20 | 1h | RO | Cap List Field (CAPLIST) Capabilities List: Indicates that the controller contains a capabilities pointer list |
19 | 0h | RO | Intrerrupt Status Field (INTR_STATUS) Interrupt Status: This bit reflects state of interrupt in the device |
18:16 | 0h | RO | Reserved Field (RESERVED2) This field is Reserved |
15:11 | 0h | RO | Reserved Field (RESERVED3) This field is Reserved |
10 | 0h | RW | Interrupt Disable Field (INTR_DISABLE) This field is Interrupt Disable |
9 | 0h | RO | Reserved Field (RESERVED4) This field is Reserved |
8 | 0h | RW | Serr Enable Field (SERR_ENABLE) SERR Enable Not implemented |
7:3 | 0h | RO | Reserved Field (RESERVED5) This field is Reserved |
2 | 0h | RW | Bme Field (BME) Bus Master Enable |
1 | 0h | RW | Mse Field (MSE) Memory Space Enable |
0 | 0h | RO | Reserved Field (RESERVED6) This field is Reserved |