Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
General Capabilities and ID Register (GEN_CAP_ID) – Offset 0
Software can read the various bytes in this register using 32-bit or 64-bit accesses.
32-bit accesses may only be done to offset 000h or 004h. 64-bit accesses may only be
done to 000h. Writes to this register will have no effect.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
63:32 | 27bc86bh | RO/V | Main Counter Tick Period (COUNTER_CLK_PER_CAP) This read-only field indicates the period at which the counter increments in femtoseconds (10^-15 seconds). The HPET timers use a 24MHz clock, which has a period of 41,666,667 femtoseconds. Therefore this register will always return 027BC86Bh when read. |
31:16 | 8086h | RO | Vendor ID (VENDOR_ID_CAP) These bits will return 8086h when read to reflect Intel as the vendor. |
15 | 1h | RO | Legacy Rout Capable (LEG_RT_CAP) This bit will always be 1 when read,indicating support for the Legacy Interrupt Rout. |
14 | 0h | RO | Reserved |
13 | 1h | RO | Counter Size (COUNT_SIZE_CAP) This bit will return 1 when read to indicate |
12:8 | 7h | RO | Number of Timers (NUM_TIM_CAP) This value in this field will be 07h to indicate support for 8 timers in the timer block. |
7:0 | 1h | RO | Revision ID (REV_ID) The value in this field will be 01h to indicate for revision 1.0 |