Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Serial ATA Capability Register 1 (SATACR1) – Offset ac
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | RSVD0 (RSVD0) Reserved |
15:4 | 4h | RO | BAR Offset (BAROFST) Indicates the offset into the BAR where the AHCI Index/Data pair are located (in Dword granularity). The Index and Data I/O registers are located at offset 10h within the I/O space defined by AIDPBA(BAR4). A value of 004h indicates offset 10h. 000h = 0h offset; 001h = 4h offset; 002h = 8h offset; 003h = Ch offset; 004h = 10h offset; ...; FFFh = 3FFFh offset (max 16 KB) |
3:0 | 8h | RO | BAR Location (BARLOC) Indicates the absolute PCI Configuration Register address of the BAR containing the Index/Data pair (in Dword granularity). The Index and Data I/O registers reside within the space defined by AIDPBA(BAR4) in the SATA controller. A value of 8h indicates offset 20h, which is AIDPBA (BAR4). 0000 - 0011b = reserved; 0100b = 10h => BAR0; 0101b = 14h => BAR1; 0110b = 18h => BAR2; 0111b = 1Ch => BAR3; 1000b = 20h => AIDPBA; 1001b = 24h => BAR5; 1010 - 1110b = reserved; 1111b = Index/Data pair in PCI Configuration space which is not supported in SATA Host Controller. |