Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Global Reset Causes 1 (GBLRST_CAUSE1) – Offset 1928
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:15 | 0h | RO | Reserved |
14 | 0h | RW/1C/V | PM Handshake Global Reset Cause (SLP_LVL_RSP_ERR) If this bit is set, the cause of the previous global reset was caused by power management handshake response failure global reset. |
13 | 0h | RW/1C/V | BSCAN Global Reset Cause (BSCAN_MODE) If this bit is set, the cause of the previous global reset was caused by BSCAN mode. |
12 | 0h | RW/1C/V | Low Power Mode Exit Global Reset Cause (LPM_FW_ERR) If this bit is set, the cause of the previous global reset was caused by low power mode exit failure. |
11:10 | 0h | RO | Reserved |
9 | 0h | RW/1C/V | ESPI Type 8 Global Reset Cause (ESPI_TYPE8) If this bit is set, the cause of the previous global reset was caused by eSPI type 8. |
8 | 0h | RW/1C/V | ESPI Type 7 Global Reset Cause (ESPI_TYPE7) If this bit is set, the cause of the previous global reset was caused by eSPI type 7. |
7:5 | 0h | RO | Reserved |
4 | 0h | RW/1C/V | PMC 3 Strike Global Reset Cause (PMC_3STRIKE) If this bit is set, the cause of the previous global reset was caused by PMC 3 strike. |
3 | 0h | RO | Reserved |
2 | 0h | RW/1C/V | Host Reset Promotion Global Reset Cause (HOST_RST_PROM) If this bit is set, the cause of the previous global reset was caused by host reset promotion. |
1 | 0h | RO | Reserved |
0 | 0h | RW/1C/V | Host Reset Timeout Global Reset Cause (HOST_RESET_TIMEOUT) If this bit is set, the cause of the previous global reset was caused by a host reset timeout. |