Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1) – Offset 10c0
This register contains misc fields used to configure power management behavior with respect to HSIO.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:12 | 0h | RO | Reserved |
11:0 | 0h | RW | HSIO Lane S0 SUS Well Power Gating Policy [11:0] (MLS0SWPGP) This is a bit per lane that controls SUS Well Power Gating for a HISO lane to be used for S0 and S0ix use models as described above in HAS. |