Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Physical Layer 32.0 GT/s Control Register (G5CTL) – Offset ae4
This is the Physical Layer 32.0 GT/s Control Register registers. Refer description for each individual field below for more details of the register functionality.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:11 | 0h | RO | Reserved (RSVD_M) Reserved |
10:8 | 0h | RO | Modified TS Usage Mode Selected (MODTSUSGSEL) Thie field indicates which Usage Mode will be used by this Downstream Port the next time the Link enters LTSSM State. |
7:2 | 0h | RO | Reserved |
1 | 0h | RO | No Equalization Needed Disable (NOEQDIS) When Clear, this Port is permitted to indicate that it does not require equalization. |
0 | 0h | RO | Equalization bypass to highest rate Disable (EQBYPDIS) When Clear, this Port indicates during Link Training that is wishes to train to the highest common link data rate and skip equalization of intermediate data rates. |