Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Alternate Protocol Selective Enable Mask Register (APSEMR) – Offset b20
This is the Alternate Protocol Selective Enable Mask Register registers. Refer description for each individual field below for more details of the register functionality.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:1 | 0h | RW/P | Alternate Protocol Selective Enable Mask - Others (APEMO) Other bits in this register represent protocols other than PCI |
0 | 1h | RW/P | Alternate Protocol Selective Enable Mask - PCI Express (APEMPCIE) The PCI Express Protocol is always index 00h. The default value of this bit is 1b (i.e., PCI Express is always enabled by default). |