Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG DEVIDLE_CONTROL (DEVIDLE_CONTROL) – Offset 24c
This register allows a device driver to enable/disable a devices entry into DevIdle. By enabling DevIdle, SW specifies that it will
not touch the device without accessing this register prior to accessing any other MMIO device register. Detailed SW DevIdle
entry/exit flows are defined in the Chassis Power Management and Device Idle PFAS specifications
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:5 | 0h | NA | reserved (reserved0) reserved |
4 | 0h | RO | intr_req_capable (intr_req_capable) Set to 1 by HW if it is capable of generating an interrupt on command |
3 | 1h | RW/1C | restore_required (restore_required) When set (by HW), SW must restore state to the IP. The state may have been |
2 | 0h | RW | devidle (devidle) SW sets this bit to 1 to move the function into the DevIdle state. Writing this |
1 | 0h | NA | intr_req (intr_req) Reserved |
0 | 0h | RO | cmd_in_progress (cmd_in_progress) HW sets this bit on a 1->0 or 0->1 transition of DEVIDLE. While set, the |