Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SET STRAP MSG DATA (SSMD) – Offset 1054
This register is used to provide a BIOS programmable sticky register which contains data that will be used in the Set-Strap type 1 msg on subsequent resets. These bits are in the resume well, so only reset on G3. The usage model is that on each reset BIOS will check the state of the processor. If the state is correct, then BIOS continues. If not, then BIOS writes the SSMD and SSMC registers and does a CF9 reset. On the reset the value of what was written to SSMD takes effect. Note that some mobile platforms force G3 on S5 requests. For those platforms, if the user/BIOS wants to have these bits set, there will be 2 resets on every power-on. If the platform accepts the default of 0 for these controls, then there is only one reset. The bits are in DSW and not RTC well because this allows a user upgrade, assuming the user unplugged the system before doing the upgrade, to revert to a setting of 0. This should reduce any interoperability concerns regarding user upgrades. The DSW bits are all cleared dsw_pok, and must not be cleared by CF9h resets.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | Reserved |
15:0 | 0h | RW/L | Set_Strap DATA (SSD) When SSMS is 1, then this data is sent in the Set-Strap msg Type 1 upon reset. This data is sent i//n the 2nd DW of data, bits 15:0. This register field is locked by the Set Strap Lock SSML.SSL bit. |