Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG SSITR (SSITR) – Offset c
The read-write SSP Interrupt Test registers should be used only for testing purposes. Writing a 1 to the test transmit FIFO request SSITR.TTFS, bit 5, will generate a non-maskable Interrupt strobe signal to the Interrupt controller, and a DMA request for the Transmit FIFO. Writing a 1 to the test receive FIFO request SSITR.TRFS, bit 6, will generate a non-maskable Interrupt strobe signal to the Interrupt controller, and a DMA request for the Receive FIFO. Writing a 1 to the test receive FIFO overrun bit SSITR.TROR, bit 7, will generate a non-maskable Interrupt strobe signal to the Interrupt controller only, no DMA request will be made. Setting any of these bits will also cause the corresponding status bit(s) to be set in the Enhanced SSP Status register (SSSR). The Interrupt and/or service request, caused by the setting of one of these test bits, will remain active until the test bit is cleared by writing a 0 it. Note that Writes to reserved bits must be zeroes, and Read value of these bits are undetermined.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:8 | 0h | RO | Reserved |
7 | 0h | RW | TROR (TROR) Test Receive FIFO overrun |
6 | 0h | RW | TRFS (TRFS) Test Receive FIFO service request |
5 | 0h | RW | TTFS (TTFS) Test Transmit FIFO service request |
4:0 | 0h | RO | Reserved |