Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Port Mapping Register (MAP) – Offset 90
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:18 | 0h | RO | Reserved |
17 | 0h | RW/O | SATA Port 1 Disable (SPD1) Similar to SPD0 but for port 1. This bit is only applicable to project(s) that has port 1 physically. |
16 | 0h | RW/O | SATA Port 0 Disable (SPD0) A 1 prevents the SATA port from being enabled via config PCS.PxE. Write of 1 to PCS.PxE has no effect when the corresponding SPD[x] bit is 1. In preventing a port(s) from being enabled, BIOS shall first configure MAP.SPDx. And only then BIOS configures the PCS.PxE. This bit is only applicable to project(s) that has port 0 physically. |
15:8 | 0h | RO | Reserved |
7:0 | 0h | RW | Port Clock Disable (PCD) When any of these bits is set to 1, the clock driven to the associated port logic is gated and will not toggle. When this bit is cleared to 0, all clocks to the associated port logic will operate normally. |