Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Extended Test Mode Register 3 (ETR3) – Offset 1048
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW/V/L | CF9h Lockdown (CF9LOCK) When set, this will lock the [quote]CF9h Global Reset[quote] bit. |
30:21 | 0h | RO | Reserved |
20 | 0h | RW/L | CF9h Global Reset (CF9GR) When this bit is set, a CF9h write of 6h or Eh will cause a Global Reset of both the Host and the ME partitions. If this bit is cleared, a CF9h write of 6h or Eh will only reset the Host partition. |
19:0 | 0h | RO | Reserved |