Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
PCI Power Management Control Status & Data Register (PMCS_DR) – Offset cc
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | Reserved |
15 | 0h | RW/V | PME STATUS (PMES) This bit is set to 1 when the function detects a wake-up event |
14:13 | 0h | RW/V | DATA SCALE (DSC) This field indicates the scaling factor to be used when interpreting the |
12:9 | 0h | RW | Data Select (DSL) This four-bit field is used to select which data is to be reported through |
8 | 0h | RW | PME Enable (PMEE) If Power Management is enabled in the NVM, writing a 1 to this bit will |
7:2 | 0h | RO | Reserved |
1:0 | 0h | RW/V | Power State (PS) This field is used both to determine the current power state of the GbE LAN Controller and to set a new power state. The values are:[BR] |