Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
I2C Interrupt Status Register (IC_INTR_STAT) – Offset 2c
Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:15 | 0h | RO | (Reserved_15_31) Reserved |
14 | 0h | RO | (Reserved_14_14) Reserved |
13 | 0h | RO | R_MASTER_ON_HOLD (R_MASTER_ON_HOLD) Indicates whether a master is holding the bus and the TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE = 1 and IC_EMPTYFIFO_HOLD_MASTER_EN = 1 |
12 | 0h | RO | Reserved |
11 | 0h | RO | R_GEN_CALL (R_GEN_CALL) Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling the controller or when the processor reads bit 0 of the IC_CLR_GEN_CALL register |
10 | 0h | RO | R_START_DET (R_START_DET) Indicates whether a START or RESTART condition has occurred on the I2C |
9 | 0h | RO | R_STOP_DET (R_STOP_DET) Indicates whether a STOP condition has occurred on the I2C interface. |
8 | 0h | RO | R_ACTIVITY (R_ACTIVITY) This bit captures the controller activity and stays set until it is cleared. There are four ways to clear it: |
7 | 0h | RO | Reserved |
6 | 0h | RO | R_TX_ABRT (R_TX_ABRT) This bit indicates if the controler, as an I2C transmitter, is unable to complete |
5 | 0h | RO | Reserved |
4 | 0h | RO | R_TX_EMPTY (R_TX_EMPTY) The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in |
3 | 0h | RO | R_TX_OVER (R_TX_OVER) Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and |
2 | 0h | RO | R_RX_FULL (R_RX_FULL) Set when the receive buffer reaches or goes above the RX_TL threshold in the |
1 | 0h | RO | R_RX_OVER (R_RX_OVER) Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master goes into idle, and when ic_en goes to 0, this interrupt is cleared. |
0 | 0h | RO | R_RX_UNDER (R_RX_UNDER) Set if the processor attempts to read the receive buffer when it is empty by reading |