Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Pad Ownership (PAD_OWN_GPP_D_2) – Offset c8
Same description as PAD_OWN_GPP_D_0, except that this register is for GPP_D[23:16].
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:30 | 0h | RO | Reserved (RSVD_0) Reserved |
29:28 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_d_23) Same description as bits [1:0] |
27:26 | 0h | RO | Reserved (RSVD_1) Reserved |
25:24 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_d_22) Same description as bits [1:0] |
23:22 | 0h | RO | Reserved (RSVD_2) Reserved |
21:20 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_d_21) Same description as bits [1:0] |
19:18 | 0h | RO | Reserved (RSVD_3) Reserved |
17:16 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_d_20) Same description as bits [1:0] |
15:14 | 0h | RO | Reserved (RSVD_4) Reserved |
13:12 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_d_19) Same description as bits [1:0] |
11:10 | 0h | RO | Reserved (RSVD_5) Reserved |
9:8 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_d_18) Same description as bits [1:0] |
7:6 | 0h | RO | Reserved (RSVD_6) Reserved |
5:4 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_d_17) Same description as bits [1:0] |
3:2 | 0h | RO | Reserved (RSVD_7) Reserved |
1:0 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_d_16) 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to GPI_STS update only. Otherwise in Host ACPI Mode, updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. No read/write restriction to the Pad Configuration register set during host ownership During host ownership, CSME and ISH do not own this pad and are not notified of the GPIO input event. |