Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Register C Flag Register (Register_C) – Offset c
RTC Index: 0Ch
Attribute: Read-Only (Writes have no effect).
Default Value: 00000000
Size: 8-bit
Lockable: No
Power Well: RTC
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7 | 0h | RO/V | Interrupt Request Flag (IRQF) Interrupt Request Flag = PF * PIE + AF * AIE + UF * UFE. This also causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST# or a read of Register C. |
6 | 0h | RO/V | Periodic Interrupt Flag (PF) Periodic interrupt Flag will be one when the tap as specified by the RS bits of register A is one. If no taps are specified, this flag bit will remain at zero. This bit is cleared upon RSMRST# or a read of Register C. |
5 | 0h | RO/V | Alarm Flag (AF) Alarm Flag will be high after all Alarm values match the current time. This bit is cleared upon RTCRST# or a read of Register C. |
4 | 0h | RO/V | Update-ended Flag (UF) Updated-ended flag will be high immediately following an update cycle for each second. The bit is cleared upon RSMRST# or a read of Register C. |
3:0 | 0h | RO | Reserved (RSVD) Will always report 0 |