Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SMI Status (GPI_SMI_STS_GPP_C_0) – Offset 278
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RO | Reserved |
23 | 0h | RW/1C | GPI SMI Status (GPI_SMI_STS_xxgpp_c_23) Same description as bit 22. |
22 | 0h | RW/1C | GPI SMI Status (GPI_SMI_STS_xxgpp_c_22) This bit is set to '1' by hardware when a level event (See RxEdCfg, RxInv) is detected, and all the following conditions are true: |
21:0 | 0h | RO | Reserved |