Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG MSR (MSR) – Offset 18
Modem Status Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:8 | 0h | RO | Reserved |
7 | 0h | RO | DCD (DCD) Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 dcd_n input is de-asserted (logic 1) 1 dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to 1), DCD is the same as MCR[3] (Out2). |
6 | 0h | RO | RI (RI) Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 ri_n input is de-asserted (logic 1) 1 ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to 1), RI is the same as MCR[2] (Out1). |
5 | 0h | RO | DSR (DSR) Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 dsr_n input is de-asserted (logic 1) 1 dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to 1), DSR is the same as MCR[0] (DTR). |
4 | 0h | RO | CTS (CTS) Clear to Send. This is used to indicate the current state of the modem control |
3 | 0h | RO | DDCD (DDCD) Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 no change on dcd_n since last read of MSR 1 change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). |
3 | 0h | NA | Reserved2 (Reserved2) Reserved |
2 | 0h | NA | Reserved1 (Reserved1) Reserved |
2 | 0h | RO | TERI (TERI) Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 no change on ri_n since last read of MSR 1 change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. |
1 | 0h | RO | DDSR (DDSR) Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 no change on dsr_n since last read of MSR 1 change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). |
1 | 0h | NA | Reserved0 (Reserved0) Reserved |
0 | 0h | RO | DCTS (DCTS) Delta Clear to Send. This is used to indicate that the modem control line cts_n |