Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Command (CMD) – Offset 4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:11 | 0h | RO | Reserved |
10 | 0h | RW | Interrupt Disable (ID) This disables pin-based INTx# interrupts. This bit has no effect on MSI operation. When set, internal INTx# will not be generated. When cleared, internal INTx# are generated if there is an interrupt and MSI is not enabled. |
9 | 0h | RO | Reserved |
8 | 0h | RW | SERR# Enable (SEE) When set to 1, the HBA is allowed to generate SERR# on DPD or SATAGC.URD event that is enabled for SERR# generation. When cleared to 0, it is not. |
7 | 0h | RO | Reserved |
6 | 0h | RW | Parity Error Response Enable (PEE) When set, the SATA Controller will corrupt the outbound DATA FIS CRC if a forwarded data parity error is indicated. |
5:3 | 0h | RO | Reserved |
2 | 0h | RW | Bus Master Enable (BME) Controls the SATA Controller's ability to act as a master for data transfers. This bit does not impact the generation of completions for split transaction commands. |
1 | 0h | RW | Memory Space Enable (MSE) Controls access to the SATA Controller's target memory space (for AHCI). |
0 | 0h | RW | I/O Space Enable (IOSE) Controls access to the SATA Controller's target I/O space. |