Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Link Capabilities Register (LNKCAP) – Offset 8c
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RW/O | Port number (PN) This field indicates the PCI Express Port number for the given PCI Express Link. Not supported. This bit is not connected to any logic. |
23:18 | 0h | RO | RESERVED (RSVD) RESERVED |
17:15 | 7h | RW/O | L1 Exit Latency (L1EL) This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported, the value is undefined. |
14:12 | 7h | RW/O | L0s Exit Latency (L0SEL) This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported, the value is undefined; |
11:10 | 0h | RO | Active State Power Management (ASPM) Support (ASPMS) This field indicates the level of ASPM supported on the given PCI Express Link. |
9:4 | 1h | RO | Maximum Link Width (MLW) This field indicates the maximum Link width (xN corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port), adapter connector (Upstream Port), or in the case of component-to-component connections, the actual wired connection width. |
3:0 | 1h | RO | Max Link Speed (MLS) This field indicates the maximum Link speed of the associated Port |