Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Interrupt Information Byte 1 (INTRB1) – Offset 3d
This is the Interrupt Information Byte 1 registers. Refer description for each individual field below for more details of the register functionality.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7:0 | 1h | RO/V | Interrupt Pin (IPIN) Indicates the interrupt pin driven by the root port. At reset, this register takes on the following values, which reflect the reset state of the STRPFUSECFG.PxIP field: |