Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Physical Layer 32.0 GT/s Capability Register (G5CAP) – Offset ae0
This is the Physical Layer 32.0 GT/s Capability Register registers. Refer description for each individual field below for more details of the register functionality.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | Reserved (RSVD_M) Reserved |
15:11 | 0h | RO | Modified TS Reserved Usage Modes (MODTSUSGMDRSVRVD) Reserved bits for future Usage Modes defined by the PCISIG. Must be 0 0000b. |
10 | 0h | RO | Modified TS Usage Mode 2 Supported - Alternate Protocol (MODTSUSGMD2SUP) This bit indicates that this Port supports sending |
9 | 0h | RO | Modified TS Usage Mode 1 Supported - Training Set Message (MODTSUSGMD1SUP) This bit indicates that this Port supports sending |
8 | 1h | RO | Modified TS Usage Mode 0 Supported - PCI Express (MODTSUSGMD0SUP) his bit indicates that this Port supports PCI Express (Modified TS Usage 000b). This bit must be 1b. |
7:2 | 0h | RO | Reserved |
1 | 0h | RO | No Equalization Needed Supported\n (NOEQSUP) When Set, this Port supports controlling whether or not Equalization is needed. |
0 | 0h | RO | Equalization bypass to highest rate Supported (EQBYPSUP) When Set, this Port supports controlling whether the Port negotiates to skip equalization for speeds other than the highest common supported speed. |