Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG LLP_HI1 (LLP_HI1) – Offset 86c
You need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the
channel if block chaining is enabled The LLP register has two functions: The logical result of the equation LLP.LOC !=
0 is used to set up the type of DMA transfer-single or multi-block. Table shows how the method of updating the channel
registers is a function of LLP.LOC != 0. If LLP.LOC is set to 0x0, then transfers using linked lists are not enabled. This register must be programmed prior to enabling the channel in order to set up the transfer type. LLP.LOC != 0 con tains
the pointer to the next LLI for block chaining using linked lists, The LLPx register can also point to the address where
write-back of the control and source/destination status information occur after block completion.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:0 | 0h | RW | LOC (LOC) Starting Address In Memory of next LLI if block chaining is enabled. Note that the |