Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
RIRB Status (RIRBSTS) – Offset 5d
This register provides the status of the Response Input Ring Buffer.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7:3 | 0h | RO | Reserved |
2 | 0h | RW/1C/V | Response Overrun Interrupt Status (RIRBOIS) Hardware sets this bit to a 1 when the RIRB DMA engine is not able to write the incoming responses to memory before additional incoming responses overrun the internal FIFO. When the overrun occurs, the hardware will drop the responses which overrun the buffer. An interrupt may be generated if the Response Overrun Interrupt Control bit is set. |
1 | 0h | RO | Reserved (RSVD11) This is a Reserved Register |
0 | 0h | RW/1C/V | Response Interrupt (RINTFL) Hardware sets this bit to a 1 when an interrupt has been generated after N number of Responses are sent to the RIRB buffer OR when an empty Response slot is encountered on all SDI[x] inputs (whichever occurs first). |