Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
RIRB Control (RIRBCTL) – Offset 5c
This register provides the control of the Response Input Ring Buffer.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7:3 | 0h | RO | Reserved |
2 | 0h | RW | Response Overrun Interrupt Control (RIRBOIC) If this bit is set (and GIE and CIE are enabled), the hardware will generate an interrupt when the Response Overrun Interrupt Status bit is set. |
1 | 0h | RW/V | RIRB DMA Enable (RIRBRUN) 0 = DMA Stop |
0 | 0h | RW | Response Interrupt Control (RINTCTL) 0 = Disable Interrupt |