Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) – Offset a0
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:22 | 0h | RO | Reserved Field (RESERVED0) This field is Reserved |
21 | 0h | RW/P | Hae Field (HAE) Hardware Autonomous Enable |
20 | 0h | RO | Reserved Field (RESERVED1) This field is Reserved |
19 | 1h | RW/P | Sleep Enable Field (SLEEP_EN) This field is Sleep Enable |
18 | 1h | RW/P | D3 Hen Field (PGE) D3-Hot Enable (D3HEN): If 1 then function will power gate when idle and the PMCSR[1:0] register in the function =11 (D3). |
17 | 1h | RW/P | Device Idle En Field (I3E) DEVIDLE Enable (DEVIDLEN): If 1 then the function will power gate when idle and the DevIdle register (DevIdleC[2] = 1) is set. |
16 | 1h | RW/P | Pmc Request Enable Field (PMCRE) PMCRE: PMC Request Enable |
15:13 | 0h | RO | Reserved Field (RESERVED2) This field is Reserved |
12:10 | 2h | RW/O/P | Power Latency Scale Field (POW_LAT_SCALE) Power On Latency Scale |
9:0 | 0h | RW/O/P | Power Latency Value Field (POW_LAT_VALUE) Power On Latency value |