Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG FCR (FCR) – Offset 8
FIFO Control Register.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:8 | 0h | NA | Res_31_8 (Res_31_8) Reserved |
7:6 | 0h | WO | RCVR (RCVR) RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the |
5:4 | 0h | WO | TET (TET) TX Empty Trigger. This is used to select the empty threshold level at which the THRE |
3 | 0h | WO | DMAM (DMAM) NA for UART IP. |
2 | 0h | WO | XFIFOR (XFIFOR) XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treatsthe |
1 | 0h | WO | RFIFOR (RFIFOR) RCVR FIFO Reset. This resets the control portion of the receive FIFO and treatsthe |
0 | 1h | WO | FIFOE (FIFOE) FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. |